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50S116T SDRAM 512K x 2 BANKS x 16 BITS SDRAM Table of Contents1. GENERAL DESCRIPTION ..................................................................................................................3 2. FEATURES ..........................................................................................................................................3 3. AVAILABLE PART NUMBER...............................................................................................................3 4. PIN CONFIGURATION........................................................................................................................4 5. PIN DESCRIPTION..............................................................................................................................5 6. BLOCK DIAGRAM ...............................................................................................................................6 7. FUNCTIONAL DESCRIPTION ............................................................................................................7 Power-up and Initialization ................................................................................................................7 Programming Mode Register............................................................................................................7 Bank Activate Command ..................................................................................................................7 Read and Write Access Modes ........................................................................................................7 Burst Read Command ......................................................................................................................8 Burst Write Command ......................................................................................................................8 Read Interrupted by a Read..............................................................................................................8 Read Interrupted by a Write..............................................................................................................8 Write Interrupted by a Write..............................................................................................................8 Write Interrupted by a Read..............................................................................................................8 Burst Stop Command .......................................................................................................................8 Addressing Sequence of Sequential Mode.......................................................................................9 Addressing Sequence of Interleave Mode ........................................................................................9 Auto Precharge Command .............................................................................................................10 Precharge Command......................................................................................................................10 Self Refresh Command ..................................................................................................................10 Power-down Mode ..........................................................................................................................10 No Operation Command.................................................................................................................11 Deselect Command ........................................................................................................................11 Clock Suspend Mode......................................................................................................................11 8. TABLE OF OPERATING MODES .....................................................................................................12 9. ELECTRICAL CHARACTERISTICS..................................................................................................13 Absolute Maximum Ratings ............................................................................................................13 Recommended DC Operating Conditions ......................................................................................13 Capacitance ....................................................................................................................................13 * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 1 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM DC Characteristics..........................................................................................................................14 AC Characteristics ..........................................................................................................................15 10. TIMING WAVEFORMS....................................................................................................................17 Command Input Timing ..................................................................................................................17 Read Timing ...................................................................................................................................18 Control Timing of Input/Output Data ...............................................................................................19 Mode Reqister Set Cycle ................................................................................................................20 11. OPERATING TIMING EXAMPLE ....................................................................................................21 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ........................................................21 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge) .............................22 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ........................................................23 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge) .............................24 Interleaved Bank Write (Burst Length = 8) .....................................................................................25 Interleaved Bank Write (Burst Length = 8, Auto Precharge) ..........................................................26 Page Mode Read (Burst Length = 4, CAS Latency = 3) .................................................................27 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) .......................................................28 Auto Precharge Read (Burst Length = 4, CAS Latency = 3) ..........................................................29 Auto Precharge Write (Burst Length = 4) .......................................................................................30 Auto Refresh Cycle .........................................................................................................................31 Self Refresh Cycle ..........................................................................................................................32 Bust Read and Single Write (Burst Lenght = 4, CAS Latency = 3).................................................33 Power-down Mode ..........................................................................................................................34 Auto Precharge Timing (Read Cycle) .............................................................................................35 Auto Precharge Timing (Write Cycle) .............................................................................................36 Timing Chart of Write-to-Read Cycle (In the case of Burst Length = 4) .........................................37 Timing Chart of Burst Stop Cycle (Burst Stop Command) .............................................................37 Timing Chart of Burst Stop Cycle (Prechare Command)................................................................38 CKE/DQM Input Timing (Write Cycle) ............................................................................................39 CKE/DQM Input Timing (Read Cycle) ............................................................................................40 Self Refresh/Power-down Mode Exit Timing ..................................................................................41 12. PACKAGE DIMENSIONS ................................................................................................................42 50L-TSOP (II) 400 mill ....................................................................................................................42 * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 2 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM 1. GENERAL DESCRIPTION 50S116T is a high-speed synchronous dynamic random access memory (SDRAM), organized as 512K words x 2 banks x 16 bits. Using pipelined architecture 50S116T delivers a data bandwidth of up to 400M bytes per second (-5). For different applications the 50S116T is sorted into the following speed grades: -5, -6, -7. The -5 parts can run up to 200MHz/CL3. The -6 parts can run up to 166 MHz/CL3. The -7 parts can run up to 143 MHz/CL3. For handheld device application. Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time. By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. 50S116T is ideal for main memory in high performance applications. 2. FEATURES * 3.3V 0.3V power supply * Up to 200 MHz clock frequency * 524,288 words x 2 banks x 16 bits organization * CAS latency: 2 and 3 * Burst Length: 1, 2, 4, 8, and full page * Burst read, Single Write Mode * Byte data controlled by UDQM and LDQM * Auto precharge and controlled precharge * 4K refresh cycles/64 mS * Interface: LVTTL * Packaged in 50-pin, 400 mil TSOP II 3. AVAILABLE PART NUMBER PART NUMBER 50S116T-5 50S116T-6 50S116T-7 SPEED (CL = 3 ) 200 MHz 166 MHz 143 MHz SELF REFRESH CURRENT(MAX.) 1 mA 1 mA 1 mA * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 3 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM 4. PIN CONFIGURATION VCC DQ0 DQ1 VSS Q DQ2 DQ3 VCCQ DQ4 DQ5 VSS Q DQ6 DQ7 VCCQ LDQM WE CAS RAS CS BA A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 VSS Q DQ13 DQ12 VCCQ DQ11 DQ10 VSS Q DQ9 DQ8 VCCQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 4 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM 5. PIN DESCRIPTION PIN NUMBER 20 - 24, 27 - 32 19 2, 3, 5, 6, 8, 9, 11, 12, 39, 40, 42, 43, 45, 46, 48, 49 18 PIN NAME A0 - A10 BA DQ0 - DQ15 FUNCTION Address DESCRIPTION Multiplexed pins for row and column address. Row address: A0-A10. Column address: A0 - A7. Bank Select Select bank to activate during row address latch time, or bank to read/write during column address latch time. Data Input/ Output Multiplexed pins for data input and output. CS Chip Select Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Row Address Command input. When sampled at the rising edge of Strobe the clock, RAS , CAS and WE define the operation to be executed. Column Address Strobe Referred to RAS RAS 17 RAS 16 CAS 15 36, 14 WE Write Enable Referred to UDQM/ LDQM Input/Output The output buffer is placed at Hi-Z (with latency of 2) Mask when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. Clock Inputs System clock used to sample inputs on the rising edge of clock. Clock Enable CKE controls the clock activation and deactivation. When CKE is low, Power-down mode, Suspend mode, or Self Refresh mode is entered. Power (+3.3V) Ground Power (+3.3V) for I/O buffer Ground for I/O buffer Power for input buffers and logic circuit inside DRAM. Ground for input buffers and logic circuit inside DRAM. Separated power from VCC, used for output buffers to improve noise immunity. Separated ground from VSS, used for output buffers to improve noise immunity. 35 34 CLK CKE 1, 25 26, 50 7, 13, 38, 44, VCC VSS VCCQ 4, 10, 41, 47 33, 37 VSSQ NC No No connection Connection * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 5 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM 6. BLOCK DIAGRAM CLK CLOCK BUFFER CKE CS RAS CAS WE COMMAND DECODER CONTROL SIGNAL GENERATOR COLUMN DECODER R O W D E C O D E R CELL ARRAY BANK #0 SENSE AMPLIFIER A10 A0 A9 BA ADDRESS BUFFER MODE REGISTER DATA CONTROL CIRCUIT DQ BUFFER DQ0 DQ15 LDQM UDQM REFRESH COUNTER COLUMN COUNTER COLUMN DECODER R O W D E C O D E R CELL ARRAY BANK #1 SENSE AMPLIFIER Note: The cell array configuration is 2048 * 256 * 16 * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 6 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM 7. FUNCTIONAL DESCRIPTION Power-up and Initialization The default power-up state of the mode register is unspecified. The following power-up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs during power-up, all VCC and VCCQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power-up voltage must not exceed VCC +0.3V on any of the input pins or VCC supplies. After power-up, an initial pause of 200 S is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power-up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation. Programming Mode Register After initial power-up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS , CAS , CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table. Bank Activate Command The Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank-to-Bank delay time (tRRD). The maximum time that each bank can be held active is specified as tRAS(max.). Read and Write Access Modes After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The address inputs determine the starting column address. Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 7 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Burst Read Command The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 1 and 2 in the next page explain the address sequence of interleave mode and sequence mode. Burst Write Command The Burst Write command is initiated by applying logic low level to CS , CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored. Read Interrupted by a Read A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command the is satisfied. Read Interrupted by a Write To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed. Write Interrupted by a Write A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. Write Interrupted by a Read A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored. Burst Stop Command A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 8 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM edge of the clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS Latency in a burst read cycle, interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored. Addressing Sequence of Sequential Mode A column access is performed by increasing the address from the column address, which is input to the device. The disturb address is varied by the Burst Length as shown in Table 1. Table 1 Address Sequence of Sequential Mode DATA Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 ACCESS ADDRESS n n+1 n+2 n+3 n+4 n+5 n+6 n+7 BL = 8 (disturb addresses are A0, A1 and A2) No address carry from A2 to A3 BURST LENGTH BL = 2 (disturb address is A0) No address carry from A0 to A1 BL = 4 (disturb addresses are A0 and A1) No address carry from A1 to A2 Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 2. Table 2 Address Sequence of Interleave Mode DATA Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 ACCESS ADDRESS A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A8 A7 A6 A5 A4 A3 A2 A8 A7 A6 A5 A4 A3 A2 A8 A7 A6 A5 A4 A3 A8 A7 A6 A5 A4 A3 A8 A7 A6 A5 A4 A3 A8 A7 A6 A5 A4 A3 A2 A2 A2 A2 A1 A1 A0 A0 A0 BL = 8 BL = 4 BUST LENGTH BL = 2 A1 A0 A1 A1 A1 A0 A0 A0 * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 9 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Auto Precharge Command If A10 is set to high when the Read or Write Command is issued, then the auto precharge function is entered. During auto precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS latency. A Read or Write Command with auto precharge can not be interrupted before the entire burst operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with auto precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto Precharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock delay from the last burst write cycle. This delay is referred to as Write tWR. The bank undergoing auto precharge can not be reactivated until tWR and tRP are satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Auto precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS(min). Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when CS , RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. The address bits, A10, and BA, are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP). Self Refresh Command The Self Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh operation after CKE is returned high. Any subsequent commands can be issued after tRC from the end of Self Refresh command. If, during normal operation, Auto Refresh cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 Auto Refresh cycles should be completed just prior to entering and just after exiting the Self Refresh mode. Power-down Mode The Power-down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power-down mode does not perform any refresh operations; therefore the device can not remain in Power-down mode longer than the Refresh period (tREF) of the device. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 10 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM The Power-down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on tCK. The input buffers need to be enabled with CKE held high for a period equal to tCKS(min) + tCK(min). No Operation Command The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS , CAS , and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS , CAS , and WE signals become don't cares. Clock Suspend Mode During normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. There is a one-clock delay between the registration of CKE low and the time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one-clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 11 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM 8. TABLE OF OPERATING MODES Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 3 shows the truth table for the operation commands. Table 3 Truth Table (Note 1, 2) COMMAND Bank Active Bank Precharge Precharge All Write Write with Auto Precharge Read Read with Auto Precharge Mode Register Set No Operation Burst Stop Device Deselect Auto Refresh Self Refresh Entry Self Refresh Exit Clock Suspend Mode Entry Power-down Mode Entry Clock Suspend Mode Exit Power-down Mode Exit DEVICE CKEn-1 STATE Idle Any Any Active (3) Active (3) Active (3) Active (3) Idle Any Active (4) Any Idle Idle Idle (S.R) Active Idle Active (5) Active Any (Powerdown) Active Active H H H H H H H H H H H H H L L H H H L L L H H CKEn X X X X X X X X X X X H L H H L L L H H H X X DQM X X X X X X X X X X X X X X X X X X X X X L H BA V V X V V V V V X X X X X X X X X X X X X X X A10 V L H L H L H V X X X X X X X X X X X X X X X A9-0 V X X V V V V V X X X X X X X X X X X X X X X CS L L L L L L L L L L H L L H L X H L X H L X X RAS L L L H H H H L H H X L L X H X X H X X H X X CAS H H H L L L L L H H X L L X H X X H X X H X X WE H L L L L H H L H L X H H X H X X H X X H X X Data Write/Output Enable Data Write/Output Disable Notes: (1) V = Valid, X = Don't care, L = Low Level, H = High Level (2) CKEn signal is input level when commands are provided. (3) These are state of bank designated by BA signals. (4) Device state is full page burst operation. (5) Power-down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 12 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM 9. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings PARAMETER Input, Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current of the device. SYMBOL VIN, VOUT VCC, VCCQ TOPR TSTG TSOLDER PD IOUT RATING -0.3 - 4.6 -0.3 - 4.6 0 - 70 -55 - 125 260 1 50 UNIT V V C C C W mA NOTE 1 1 1 1 1 1 1 Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability Recommended DC Operating Conditions (TA = 0 to 70C) PARAMETER Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input High Voltage Input Low Voltage SYM. VCC VCCQ VIH VIL MIN. 3.0 3.0 2.0 -0.3 TYP. 3.3 3.3 - MAX. 3.6 3.6 VCC +0.3 0.8 UNIT V V V V NOTE 2 2 2 2 Note: VIH (max.) = VCC/VCCQ +1.2V for pulse width < 5 nS VIL (min.) = VSS/VSSQ -1.2V for pulse width < 5 nS Capacitance (VCC = 3.3V, TA = 25 C, f = 1MHz) PARAMETER Input Capacitance (A0 to A10, BA, WE , UDQM, LDQM, CKE) Input Capacitance (CLK) Input/Output capacitance (DQ0 to DQ15) Note: These parameters are periodically sampled and not 100% tested SYM. RAS , CAS , CI MIN. - MAX. 5 5 7 UNIT pf pf pf CS , CIO - * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 13 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM DC Characteristics (VCC = 3.3V 0.3V, TA = 0~70C) PARAMETER Operating Current tCK = min., tRC = min. Active precharge command cycling without burst operation Standby Current tCK = min., CS = VIH VIH /L = VIH (min.) /VIL (max.) Bank: inactive state Standby Current CLK = VIL, CS = VIH VIH/L = VIH (min.) /VIL (max.) Bank: inactive state No Operating Current tCK = min., CS = VIH (min.) Bank: active state (2 banks) Burst Operating Current min.) Read/ Write command cycling Auto Refresh Current min.) Auto refresh command cyclin Self Refresh Current (CKE = 0.2V) Self refresh mode Standrad (tCK = CKE = VIH 1 bank operation SYM. ICC1 -5 MAX. 70 -6 MAX. 60 -7 MAX. 50 UNIT NOTES 3 CKE = VIH CKE = VIL (Power-down mode) ICC2 ICC2P 35 1 30 1 25 1 3 3 ICC2S 8 8 8 CKE = VIL (Power-down mode) ICC2PS ICC3 ICC3P ICC4 1 45 3 120 1 40 3 110 1 35 3 100 mA CKE = VIH CKE = VIL (Power-down mode) (tCK = 3, 4 ICC5 60 55 50 3 ICC6 1 1 1 PARAMETER Input Leakage Current (0V VIN VCC, all other pins not under test = 0V) Output Leakage Current (Output disable , 0V VOUT VCCQ ) LVTTL OutputT H Level Voltage (IOUT = -2 mA) LVTTL Output L Level Voltage (IOUT = 2 mA) SYM. II IO MIN. -10 -10 MAX. 10 10 UNIT A A V NOTES VOH 2.4 - VOL - 0.4 V * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 14 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM AC Characteristics (VCC = 3.3V 0.3V, VSS = 0V, TA = 0 to 70 C, Notes: 5, 6, 7, 8) PARAMETER SYM. MIN. -5 MAX. MIN. 60 100000 42 18 1 18 12 8 6 1000 1000 8 6 2 2 5.5 4.5 -6 MAX. MIN. 65 100000 45 20 1 20 14 10 7 1000 1000 10 7 2.5 2.5 6 5 2 5 2 1 5 10 1 0.5 1.5 1 1.5 1 1.5 1 1.5 1 64 64 12 14 6 10 6 2.5 2.5 1 1 0.5 1.5 1 1.5 1 1.5 1 1.5 1 -7 MAX. UNIT Ref/Active to Ref/Active Command Period Active to Precharge Command Period tRC tRAS 54 40 15 1 15 10 7 5 nS 100000 Active to Read/Write Command Delay Time tRCD Read/Write(a) to Read/Write(b)Command Period Precharge to Active(b) Command Period Active(a) to Active(b) Command Period Write Recovery Time CL* = 2 CL* = 3 CLK Cycle Time CL* = 2 CL* = 3 CLK High Level Width CLK Low Level Width Access Time from CLK CL* = 2 CL* = 3 Output Data Hold Time Output Data High Impedance Time Output Data Low Impedance Time Power-down Mode Entry Time Transition Time of CLK (Rise and Fall) Data-in-Set-up Time Data-in Hold Time Address Set-up Time Address Hold Time CKE Set-up Time CKE Hold Time Command Set-up Time Command Hold Time Refresh Time Mode Register Set Cycle Time tOH tHZ tLZ tSB tT tDS tDH tAS tAH tCKS tCKH tCMS tCMH tREF tRSC tCH tCL tAC tCK tCCD tRP tRPD tWR Cycle nS 7 5 2 2 1000 1000 6.5 5.5 1.8 1.5 1 1 0.5 1.5 1 1.5 1 1.5 1 1.5 1 7 7 10 64 mS nS 10 * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 15 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Notes: 1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices. 2. All voltages are referenced to VSS 3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of tCK and tRC. 4. These parameters depend on the output loading conditions. Specified values are obtained with output open. 5. Power-up sequence is further described in the "Functional Description" section. 6. AC test conditions. PARAMETER Output Reference Level Output Load Input Signal Levels Transition Time (Rise and Fall) of Input Signal Input Reference Level CONDITIONS 1.4V/1.4V See diagram below 2.4V/0.4V 2 nS 1.4V 1.4 V 50 ohms output Z = 50 ohms 30pF AC TEST LOAD 7. Transition times are measured between VIH and VIL. 8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 16 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM 10. TIMING WAVEFORMS Command Input Timing tCK tCL tCH VIH CLK VIL tT tCMS tCMH tCMH tT tCMS CS tCMS tCMH RAS tCMS tCMH CAS tCMS tCMH WE tAS tAH A0-A10 BA tCKH tCKS tCKH tCKS tCKS tCKH CKE * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 17 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Timing Waveforms, continued Read Timing Read CAS Latency CLK CS RAS CAS WE A0-A10 BA tAC tLZ tOH Valid Data-Out tAC tHZ tOH Valid Data-Out DQ Read Command Burst Length * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 18 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Timing Waveforms, continued Control Timing of Input/Output Data Input Data (Word Mask) CLK tCMH tCMS tCMH tCMS DQM tDS tDH Valid Data-in tDS tDH Valid Data-in tDS tDH Valid Data-in tDS tDH Valid Data-in DQ0 -15 (Clock Mask) CLK tCKH tCKS tCKH tCKS CKE tDS tDH Valid Data-in tDS tDH Valid Data-in tDS tDH Valid Data-in tDS tDH Valid Data-in DQ0 -15 Output Data (Output Enable) CLK tCMH tCMS tCMH tCMS DQM tAC tOH tOH tAC tHZ tOH Valid Data-Out tAC tLZ tOH Valid Data-Out tAC DQ0 -15 Valid Data-Out OPEN (Clock Mask) CLK tCKH tCKS tCKH tCKS CKE tAC tOH tOH Valid Data-Out Valid Data-Out tAC tOH tAC tOH Valid Data-Out tAC DQ0 -15 * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 19 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Timing Waveforms, continued Mode Reqister Set Cycle tRSC CLK tCMS tCMH CS tCMS tCMH RAS tCMS tCMH CAS tCMS tCMH WE tAS tAH Register set data A0-A10 BA A0 A1 A2 A3 A4 A5 A6 A7 A0 A8 A9 A0 A10 BA "0" "0" A0 Reserved "0" "0" (Test Mode) Reserved Write Mode A0 CAS Latency Addressing Mode Burst Length A2 0 0 0 0 1 1 1 1 A1 A0 0 A0 0 A0 1 A0 1 A0 0 A0 0 A0 1 A0 1 A3 A0 0 A0 1 A0 0 1 0 1 0 1 0 1 next command Burst Length A0 A0 Sequential Interleave 1 1 2 2 4 4 A0 8 8 Reserved FullA0 Page Addressing Mode Sequential Interleave CAS Latency Reserved A0 Reserved 2 3 Reserved Single Write Mode Burst read and Burst write Burst read and single write Reserved A6 0 0 0 0 1 A0 A5 A4 A0 0 0 0 1 1 0 1 1 0 0 A9 0 1 * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 20 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM 11. OPERATING TIMING EXAMPLE Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC tRAS tRP tRP tRAS RAS tRAS tRP tRAS CAS WE BA tRCD tRCD RBb RAc tRCD RBd tRCD RAe A10 RAa A0-A9 DQM RAa CAw RBb CBx RAc CAy RBd CBz RAe CKE tAC tAC aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 tAC cy0 cy1 cy2 cy3 tAC DQ tRRD tRRD tRRD tRRD Bank #0 Active Bank #1 Read Active Precharge Read Active Read Precharge Active Precharge Read Active * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 21 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Operating Timing Example, continued Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC tRAS tRP tRP tRAS RAS tRAS tRP tRAS CAS WE BA tRCD tRCD RBb RAc tRCD tRCD RBd RAe A10 RAa A0-A9 DQM CKE RAa CAw RBb CBx RAc CAy RBd CBz RAe tAC tAC aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 tAC cy0 cy1 cy2 cy3 tAC dz0 DQ tRRD tRRD tRRD tRRD Bank #0 Bank #1 Active Read Active AP* Read Active Read AP* Active AP* Read Active * AP is the internal precharge start timing * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 22 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Operating Timing Example, continued Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC RAS tRAS tRP tRP tRAS tRAS tRP CAS WE BA tRCD tRCD RBb RAc tRCD A10 RAa A0-A9 DQM RAa CAx RBb CBy RAc CAz CKE tAC tAC ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 tAC by7 CZ0 DQ tRRD tRRD Bank #0 Bank #1 Active Read Precharge Active Read Precharge Active Read Precharge * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 23 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Operating Timing Example, continued Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 tRC 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP tRAS tRAS tRP CAS WE BA tRCD tRCD RBb RAc tRCD A10 RAa A0-A9 DQM RAa CAx RBb CBy RAc CAz CKE DQ tCAC ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 tCAC tCAC by4 by5 by6 CZ0 by0 by1 tRRD tRRD Bank #0 Bank #1 Active Read Active AP* Read Active Read AP* * AP is the internal precharge start timing * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 24 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Operating Timing Example, continued Interleaved Bank Write (Burst Length = 8) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS t RP tRAS tRAS tRP CAS tRCD tRCD tRCD WE BA A10 RAa RBb RAc A0-A9 DQM RAa CAx RBb CBy RAc CAz CKE DQ ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD t RRD Bank #0 Bank #1 Active Write Active Write Precharge Active Write Precharge * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 25 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Operating Timing Example, continued Interleaved Bank Write (Burst Length = 8, Auto Precharge) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP tRAS CAS WE BA tRCD tRCD RBb RAb tRCD A10 RAa A0-A9 DQM CKE DQ RAa CAx RBb CBy RAb CAz ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD tRRD Bank #0 Active Bank #1 Write Active AP* Write Active Write AP* * AP is the internal precharge start timing * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 26 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Operating Timing Example, continued Page Mode Read (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tCCD tCCD tCCD tRP tRAS tRP CS tRAS RAS CAS WE BA tRCD tRCD RBb A10 A0-A9 DQM CKE RAa RAa CAI RBb CBx CAy CAm CBz tAC tAC a0 a1 a2 a3 bx0 bx1 tAC tAC tAC am0 am1 am2 bz0 bz1 bz2 bz3 DQ tRRD Ay0 Ay1 Ay2 Bank #0 Bank #1 Active Read Active Read Read Read Read Precharge AP* * AP is the internal precharge start timing * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 27 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Operating Timing Example, continued Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS tRAS tRP WE BA tRCD A10 RAa A0-A9 RAa CAx CAy DQM CKE tAC tWR ax0 ax1 ax2 ax3 ax4 ax5 ay0 ay1 ay2 ay3 ay4 DQ Q Q Q Q D D D D D Bank #0 Bank #1 Active Read Write Precharge * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 28 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Operating Timing Example, continued Auto Precharge Read (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS tRC tRC RAS tRAS tRP tRAS tRP CAS WE BA tRCD tRCD RAb A10 RAa A0-A9 DQM CKE RAa CAw RAb CAx tAC tAC aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 DQ Bank #0 Bank #1 Active Read AP* Active Read AP* * AP is the internal precharge start timing * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 29 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Operating Timing Example, continued Auto Precharge Write (Burst Length = 4) (CLK = 100 MHz) CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS tRC tRC RAS tRAS tRP tRAS tRP CAS WE BS0 BS1 tRCD tRCD RAb RAc A10 A0-A9, A11 DQM CKE DQ RAa RAa CAw RAb CAx RAc aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 Bank #0 Bank #1 Active Write AP* Active Write AP* Active * AP is the internal precharge start timing * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 30 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Operating Timing Example, continued Auto Refresh Cycle (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tRP tRC tRC CS RAS CAS WE BA A10 A0-A9 DQM CKE DQ All Banks Prechage Auto Refresh Auto Refresh (Arbitrary Cycle) * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 31 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Operating Timing Example, continued Self Refresh Cycle (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRP RAS CAS WE BA A10 A0-A9 DQM tSB tCKS tCKS CKE tCKS DQ tRC Self Refresh Cycle All Banks Precharge No Operation Cycle Self Refresh Entry Arbitrary Cycle * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 32 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Operating Timing Example, continued Bust Read and Single Write (Burst Lenght = 4, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS tRCD WE BA A10 RBa A0-A9 DQM CKE RBa CBv CBw CBx CBy CBz tAC tAC av0 Q av1 Q av2 Q av3 Q aw0 D ax0 D ay0 D az0 Q az1 Q az2 Q az3 Q DQ Bank #0 Active Bank #1 Read Single Write Read * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 33 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Operating Timing Example, continued Power-down Mode (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS WE BA A10 RAa RAa A0-A9 RAa CAa RAa CAx DQM tSB tSB CKE tCKS tCKS ax0 ax1 ax2 tCKS ax3 tCKS DQ Active NOP Read Active Standby Power Down mode Precharge NOPActive Precharge Standby Power Down mode Note: The PowerDown Mode is entered by asserting CKE "low". All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode. When CKE goes high, command input must be No operation at next CLK rising edge. * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 34 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Operating Timing Example, continued Auto Precharge Timing (Read Cycle) 0 (1) CAS Latency=2 ( a ) burst length = 1 Command 1 AP 2 3 Act 4 5 6 7 8 9 10 11 Read tRP DQ ( b ) burst length = 2 Command DQ ( c ) burst length = 4 Command DQ ( d ) burst length = 8 Command DQ Q0 Read AP Q0 Read Q0 Read Q0 Q1 Q2 Q3 Q4 Q5 Q1 tRP Act Q1 AP Q2 tRP Act Q3 AP Q6 tRP Act Q7 (2) CAS Latency=3 ( a ) burst length = 1 Command Read AP tRP Act Q0 DQ ( b ) burst length = 2 Command DQ Read AP Q0 tRP Act Q1 AP tRP ( c ) burst length = 4 Command DQ Read Q0 Read Q0 Act Q3 AP tRP Q1 Q2 ( d ) burst length = 8 Command Act Q7 DQ Q1 Q2 Q3 Q4 Q5 Q6 Note: Read AP Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least tRAS(min). * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 35 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Operating Timing Example, continued Auto Precharge Timing (Write Cycle) 0 (1) CAS Latency = 2 ( a ) burst length = 1 Command 1 2 3 4 5 6 7 8 9 10 11 Write tWR AP tRP Act DQ ( b ) burst length = 2 Command D0 Write tWR AP tRP Act DQ ( c ) burst length = 4 Command D0 Write D1 AP tWR tRP Act DQ ( d ) burst length = 8 Command D0 Write D1 D2 D3 AP tWR tRP Act DQ D0 Write tWR D1 AP D2 D3 D4 Act D5 D6 D7 (2) CAS Latency = 3 ( a ) burst length = 1 Command tRP DQ ( b ) burst length = 2 Command D0 Write tWR AP tRP Act DQ ( c ) burst length = 4 Command D0 Write D1 AP tWR tRP Act DQ ( d ) burst length = 8 Command D0 Write D1 D2 D3 AP tWR tRP Act DQ D0 D1 D2 D3 D4 D5 D6 D7 Note: Write AP Act represents the Write with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least tRAS(min). * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 36 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Operating Timing Example, continued Timing Chart of Write-to-Read Cycle (In the case of Burst Length = 4) 0 (1) CAS Latency = 2 ( a ) Command DQM DQ ( b ) Command DQM DQ 1 2 3 4 5 6 7 8 9 10 11 Write D0 Write D0 Read Q0 Read D1 Q0 Q1 Q2 Q3 Q1 Q2 Q3 (2) CAS Latency = 3 ( a ) Command DQM DQ ( b ) Command DQM DQ Write D0 Write D0 Read Q0 Read D1 Q0 Q1 Q2 Q3 Q1 Q2 Q3 Timing Chart of Burst Stop Cycle (Burst Stop Command) 0 (3) Read cycle ( a ) CAS latency =2 Command DQ 1 2 3 4 5 6 7 8 9 10 11 Read Q0 Read Q0 Write D0 D1 D2 D3 D4 Q1 Q1 Q2 BST Q3 BST Q2 BST Q3 Q4 Q4 ( b ) CAS latency = 3 Command DQ (2) Write cycle Command DQ Note: BST represents the Burst stop command * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 37 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Operating Timing Example, continued Timing Chart of Burst Stop Cycle (Prechare Command) (In the case of Burst Length = 8) 0 (1) Read cycle ( a ) CAS latency = 2 Commad 1 2 3 4 5 6 7 8 9 10 11 Read Q0 Read Q0 Q1 Q1 Q2 PRCG Q3 PRCG Q2 Q3 Q4 Q4 DQ ( b ) CAS latency = 3 Commad DQ (2) Write cycle ( a ) CAS latency = 2 Commad DQM DQ Write D0 Write D1 D2 D3 D4 PRCG tWR ( b ) CAS latency = 3 Commad PRCG tWR D1 PRCG DQM DQ D0 Note: D2 D3 D4 represents the Precharge command * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 38 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Operating Timing Example, continued CKE/DQM Input Timing (Write Cycle) CLK cycle No. External CLK Internal CKE DQM DQ 1 2 3 4 5 6 7 D1 D2 D3 DQM MASK (1) D5 CKE MASK D6 CLK cycle No. External CLK Internal CKE DQM DQ 1 2 3 4 5 6 7 D1 D2 D3 DQM MASK (2) CKE MASK D5 D6 CLK cycle No. External CLK Internal CKE DQM DQ 1 2 3 4 5 6 7 D1 D2 D3 CKE MASK (3) D4 D5 D6 * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 39 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Operating Timing Example, continued CKE/DQM Input Timing (Read Cycle) CLK cycle No. 1 2 3 4 5 6 7 External CLK Internal CKE DQM DQ Q1 Q2 Q3 Q4 Open Open Q6 (1) CLK cycle No. 1 2 3 4 5 6 7 External CLK Internal CKE DQM DQ Q1 Q2 Q3 Q4 Open Q6 (2) CLK cycle No. 1 2 3 4 5 6 7 External CLK Internal CKE DQM DQ Q1 Q2 Q3 Q4 Q5 Q6 (3) * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 40 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM Operating Timing Example, continued Self Refresh/Power-down Mode Exit Timing Asynchronous Control Input Buffer turn on time ( Power down mode exit time ) is specified by CKS(min) + tCK(min) t A ) tCK < tCKS(min)+tCK(min) tCK CLK CKE tCKS(min)+tCK(min) Command NOP Command Input Buffer Enable B) tCK >= tCKS(min) + tCK (min) tCK CLK CKE tCKS(min)+tCK(min) Command Command Input Buffer Enable Note ) All Input Buffer(Include CLK Buffer) are turned off in the Power Down mode and Self Refresh mode NOP Command Represents the No-Operation command Represents one command * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 41 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 50S116T SDRAM 12. PACKAGE DIMENSIONS 50L-TSOP (II) 400 mill 50 26 E HE 1 e D b 25 C q A2 ZD L A L1 Y SEATING PLANE A1 Controlling Dimension: Millimeters DIMENSION(MM) SYM. DIMENSION (INCH) MIN. NOM. MAX. 0.047 0.006 0.043 0.018 0.008 0.830 0.405 0.471 0.024 0.004 0.031 0o 10 o MIN. NOM. MAX. 1.20 0.15 1.10 0.45 0.20 21.08 10.29 11.96 0.60 0.10 A A1 A2 b c D E HE e L L1 Y ZD 0.40 0.05 0.90 0.30 0.10 20.82 10.03 11.56 0.10 1.00 0.15 20.95 10.16 11.76 0.80 0.50 0.80 0.88 0o 0.002 0.035 0.012 0.004 0.820 0.395 0.455 0.016 0.004 0.039 0.006 0.825 0.400 0.463 0.031 0.020 0.031 10 o * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Page 42 of 42 Rev 1.0 Aug.20,2002 Fax:886-3-3521052 |
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